1. Field of the Invention
The present invention relates to an apparatus and method generating an error flag for error correction.
2. Description of the Related Art
To store information in an optical recording medium such as CD or DVD, error-correction coding (ECC) is performed in which parity data is added to user data to generate a codeword and the codeword is processed according to a predetermined method. If the user data is 30 bytes, the parity data is 30 bytes, and accordingly one codeword is 60 bytes, error correction is possible although errors are generated in maximal 15 bytes of one codeword when decoding is performed. However, if an error flag indicating the location of data including an error in the codeword is provided, error correction is possible although errors are generated in maximal 30 bytes of the codeword.
Such a technique that improves error correction performance using an error flag is called erasure correction. The erasure correction has higher error correction efficiency where a burst error is generated rather than a random error.
U.S. Pat. No. 6,367,049 discloses an error correction format consisting of a plurality of ECC (Error Correction Code) columns and a plurality of BIS (Burst Indicator Subcode) columns. BIS is information that is inserted when decoding is performed, in order to indicate the generation of a burst error. A reliability of a decoded BIS is higher than that of ECC.
FIG. 1 is a view showing a data block with an error correction format disclosed in the above-described U.S. Pat. No. 6,367,049.
According to the error correction format, in one data block, frame synchronization (frame-sync) data is included in the heading of the data block, and subsequently 38 ECC columns and one BIS column are located alternately. One data block has 496 frames. Data constructing the data block is interleaved according to a predetermined method. The detailed descriptions related to the error correction format and interleaving are disclosed in the above-described U.S. patent application Ser. No. 6,367,049.
FIG. 2 shows a detailed structure of one frame forming part of the data block of FIG. 1.
Referring to FIG. 2, in one frame, frame-sync data is included in the heading of the frame and subsequently 38-byte ECC and one-byte BIS are located alternately.
However, an error correction system according to the error correction format shown in FIGS. 1 and 2 has problems in that an interleaving process is complex, accordingly the generation of an error flag for erasure correction is not easy, and a hardware structure is complicated.